1. Field of the Invention
The present invention is generally related to the manufacturing field of semiconductor devices, and particularly to a method for Chip Scale Package (CSP) and a package structure thereof.
2. Description of Prior Art
With the continuous development in integrated circuit technology, electronic products are increasingly developing in a direction of miniaturization, intellectualization, high-performance and high-reliability. Integrated circuit (IC) package not only has direct influence on the performance of integrated circuit, electronic module and even the whole machine, but also restricts the miniaturization of the whole electronic system, the low-cost and reliability. Due to the narrowing size of integrated circuit wafers and the improving level of integration, electronic industry has made higher and higher requirements on IC package technology.
Under these circumstances, electronic industry has made higher and higher requirements on IC package technology. Therefore, integrated circuit fabrication is miniaturized, which causes a rise in logic circuits contained in the chips, and increases the number of chip input/output (I/O) pin. To meet the demands, many different methods for package come into being, such as Ball Grid Array (BGA), Chip Scale Package (CSP), Multi Chip Module package (MCM package), Flip Chip Package, Tape Carrier Package (TCP), Wafer Level Package (WLP), etc.
No matter which one is used, most of the methods for package tend to accomplish the package process after detaching wafer into separate chips, which is Chip Scale Package (CSP). CSP forms a connection between an overturned chip and a base plate through a solder ball which formed on the surface of the chip, and thus reduces the package size, meets the needs of high-performance (such as high speed, high frequency and smaller pins) and small outline of electronic products and makes the products have excellent electronic and heat-transfer properties.
Bump formation technology is a key technology in CSP. Usually the breakdown of CSP is caused by the failure of bumps, so the reliability of the bumps is the main problem to be solved in the development of CSP technology. In the prior art, solder deposits on a piece of chip metal bedding through some certain technological processes. Bumps are the metal solder balls formed after reflowing under certain temperature.
With the increasing integration of semiconductor devices, distances between bumps decrease rapidly. Bumps at the edge are liable to peel off because the edges of the chip are far from the central point, and in conditions of periodic variation of temperature, the stress on the bumps at the edge is greater than that closer to the central point. In order to maintain the mechanical intensity of a bump, volume of the bump needs to be enlarged. However, due to the mutual soluble physical property of metals, increasing volume of all bumps in limited area will make the bumps become larger and turn to a lateral move. This may cause bridging between bumps, then leads to further short-circuit, and finally influence the electrical property of semiconductor devices.